A typical successive approximation register (SAR) ADC includes capacitive digital-to-analog converter (CDAC) for performing a successive approximation of a sampled input signal. The CDAC includes an array of capacitors, where each capacitor can be assigned to a bit of the digital output word of the SAR ADC. Generally, the capacitors can be commonly coupled at a common node, which can be coupled to an input of a comparator. During each conversion step, the comparator 110 are its input signals and provides a bit of a digital output word to a control stage or SAR controller. Each of the capacitors of the CDAC are then switched in accordance with the comparison result.
Additionally, the capacitors of the CDAC may be further subdivided in to two or more stages. For example, there may be a first stage or main CDAC that includes capacitors relating to the most significant bits (MSBs) of the digital output word of the SAR ADC and a second stage or sub-CDAC that includes capacitors related to the least significant bits (LSBs) of the digital output word of the SAR ADC. There may also be a serial capacitor coupling the main CDAC and the sub-CDAC for scaling the two stages for approximation steps relating to the MSBs and the LSBs, respectively. The absolute capacitance values in the two stages may also be almost similar. However, in order to achieve high resolution, and good linearity, the matching of the capacitance values is important.
With the typical matching constraints of capacitance values in a semiconductor (e.g., CMOS) technology, a resolution of the SAR ADC of about 10 to 12 bit can be achieved. For higher resolution the capacitors mismatch has to be adjusted. The digital output word of the SAR ADC can be digitally corrected by adding or subtracting digital correction values in order to compensate static mismatch of the capacitance values. However, this approach is only applicable as long as the successive approximation process converges. Convergence generally means that at the end of the conversion procedure, a voltage difference at the comparator input is equal to or smaller than the value that corresponds to an LSB. If mismatch becomes too large, digital correction becomes impossible. Therefore, the capacitance values in the main CDAC have to be physically trimmed after production in order to achieve improved matching and to guarantee convergence of the successive approximation process. Ideal convergence generally means that the voltage difference between the comparator inputs corresponds to a value that is smaller than +/−½ LSB. The capacitors in the sub-CDAC (relating to the LSBs) are usually not trimmed after production of the integrated circuit.
There are several different principals which can be applied for trimming the capacitors of the main-CDAC. One is based on laser trimming, where capacitor values are added or subtracted from the capacitor array by use of laser beam, which removes connections in a prior assembly step. Another principle is based on adding or subtracting capacitors to and from the capacitor array based on setting switches and storing the appropriate states of the switches in a memory. Both techniques may use a self calibration procedure which aims to determine the amount of mismatch of the capacitors indicating the capacitance values which are to be added or subtracted from the capacitors of the main CDAC. However, both trimming and calibration procedures require a rather complex production step, which increases production costs. Furthermore, the trimming process for correcting the capacitance values of the main CDAC based on switches and capacitors and a memory requires a large amount of additional chip area for the switches and the memory.
U.S. Pat. No. 6,747,589 generally discloses a dynamic error correction step for an SAR ADC in order to increase speed and reduce current drive requirements of the SAR ADCs. The basic idea consists in testing a bit decision as to whether or not the error is below a maximum admissible limit. Testing and correction is performed quasi-simultaneously by selectively coupling one or two additional correction capacitors of the same size as the capacitor of the tested bit. The two additional correction capacitors are switched between the reference voltages in order to add or subtract a charge value to the network, which is equivalent to a certain bit capacitor and the output of the comparator is used as an indicator of the error. The correction capacitors provide that the successive approximation process converges. However, the digital output word of the SAR ADC is corrected by adding or subtracting single bits corresponding to the corrected position and the mismatch of the capacitance values of the capacitors is removed by trimming procedures as described above.
There are more and less significant bits in a digital output word of a SAR ADC, and corresponding more or less significant capacitors in the CDAC. The significance of a capacitor is not strictly related to its capacitance value, but rather to its contribution to the voltage level on the comparator input (common node). This contribution can be considered as a difference voltage or voltage step ΔV on a node, typically on the common node. The more significant bits of a digital output word are determined earlier than less significant bits during the successive approximation process. Therefore, the capacitor(s) are also used in order of their significance starting with the most significant capacitor and ending with the least significant capacitor(s).
In an integrated circuit or IC, the maximum and the minimum physical size of a capacitor is limited. The upper limit is due to chip costs due to chip area and the lower limit due to technological boundaries, as minimum structure size and parasitic effects. Therefore, the minimum and maximum capacitance value of a capacitor should remain within reasonable limits.